1. Field of the Invention
The present invention relates to a configuration of a data output portion of a semiconductor integrated circuit device, and more particularly, to a configuration of a data output circuit and an arrangement of power supply interconnection lines therefor in a semiconductor memory device.
2. Description of the Background Art
FIG. 18 schematically shows a chip layout of a general 4 M bit DRAM (Dynamic Random Access Memory). Referring to FIG. 18, memory cell groups 2a, 2b are disposed inside a semiconductor chip 1. Memory cell groups 2a, 2b include, although not clearly shown, a plurality of dynamic type memory cells disposed in rows and columns.
At a circumferential end of semiconductor chip 1. (right upper end portion of the chip in FIG. 18), provided is a ground potential pad 3 receiving a ground potential GND. To ground potential pad 3 connected is a ground line 4 transmitting the ground potential, which is formed of a low resistance conductor such as aluminum, and which is disposed in a loop manner along a circumference of semiconductor chip 1.
Along the circumference of semiconductor chip 1, data output portions 5a, 5b, 5c and 5d are disposed for providing data of a memory cell selected from memory cell groups 2a, 2b. In FIG. 18, it is shown that each of data output portions 5a to 5d includes a data output pad and a data output circuit. Data output portions 5a to 5d are supplied with the ground potential from ground line 4, so that, in accordance with applied memory cell data, a corresponding data output node is discharged to the ground potential.
When the data output circuit is operated at a high speed for a high speed operation of the DRAM, undershoot and/or ringing occurs at the data output node, which in turn makes an access time longer (time required for stability of the output data becomes longer). Therefore, various configurations for preventing occurrence of such undershoot and/or ringing without impairing a high speed operation performance have been invented.
FIG. 19 shows a possible configuration of a data output portion for preventing the undershoot/overshoot problem as described above. Since data output portions 5a to 5d have the same configuration, data output portion 5 is representatively shown in FIG. 19.
Data output portion 5 includes a data output circuit 13, a pad 14 for transmitting output data Dour of data output circuit 13 outside, and a pin terminal 15. Data output circuit 13 operates using a power supply potential Vcc applied to a power supply potential node 11 and a ground potential GND applied to a ground potential node 12 as an operation power source. Data output circuit 13 is activated in response to an output enable signal OEM to provide the output data Dour of the same logic level as that of an inversion signal ZDD of data read from a selected memory cell through pad 14 and pin terminal 15.
Data output circuit 13 includes an inverter 13a receiving the data inversion signal ZDD, a 2-input AND circuit 13b providing a signal .phi.1 upon receiving the output of inverter 13a and the output enable signal OEM, and an n channel MOS transistor 13c receiving the output .phi.1 of AND circuit 13b at its gate. AMOS transistor 13d is rendered conductive when the signal .phi.1 is at a logic high or "H" level to be supplied with a current from power supply potential node 11 to charge an output node 13d to a level of the power supply potential Vcc (more exactly Vcc-Vth, where vth represents a threshold voltage of transistor 13c).
Data output circuit 13 further includes an AND circuit 13e providing a signal .phi.2 upon receiving the output enable signal OEM and the data inversion signal ZDD, a delay circuit 13g delaying the output .phi.2 of AND circuit 13e by a predetermined time, and a 2-input AND circuit 13h providing a signal .phi.4 upon receiving the output .phi.2 of AND circuit 13e and an output .phi.3 of delay circuit 13g. Delay circuit 13g includes, for example, an even number of cascaded inverters (four inverters in FIG. 19).
Data output circuit 13 further includes an n channel MOS transistor 13f discharging the output node 13d to a potential level of ground potential node 12 in response to the output .phi.2 of AND circuit 13e, and an n channel MOS transistor 13i discharging output node 13d to a potential level of ground potential node 12 in response to the output .phi.4 of AND circuit 13h. MOS transistor 13i has a size and a current driving ability larger than those of MOS transistor 13f. Description will now be given to operations of data output circuit 13 shown in FIG. 19 with reference to FIGS. 20 and 21 which are operating waveform diagrams thereof. FIG. 20 shows operating waveforms when the inversion signal ZDD is at a logic low or "L" level, and FIG. 21 shows operating waveforms when the inversion signal ZDD is at an "H" level.
When data of the selected memory cell is at an "H" level, the inversion signal ZDD of the data is at an "L" level as shown in FIG. 20(a). AND circuit 13e receiving the inversion signal ZDD of an "L" level provides the output signal .phi.2 of an "L" level as shown in FIG. 20(d), independent of the level of the output enable signal OEM which is another input. N channel MOS transistor 13f receiving the output signal .phi.2 at the gate electrode is rendered non-conductive. AND circuit 13h receiving the output signal .phi.2 of an "L" level provides the output signal .phi.4 of an "L" level, as shown in FIG. 20(f), to the gate electrode of n channel MOS transistor 13i independent of the level of the delay signal .phi.3 from delay circuit 13g, whereby n channel MOS transistor 13i is rendered non-conductive.
Until the output enable signal OEM rises to an "H" level at a time t0 as shown in FIG. 20(b), AND circuit 13b receiving the output enable signal OEM of an "L" level provides the output signal .phi.1 of an "L" level, as shown in FIG. 20(c), to render n channel MOS transistor 13c receiving the output signal .phi.1 at the gate electrode non-conductive. Since n channel MOS transistors 13f and 13i are non-conductive, the data Dout provided from output node 13d is in a high impedance state.
When the output enable signal OEM rises to an "H" level at the time t0 as shown in FIG. 20(b), AND circuit 13b receiving the output enable signal OEM and an inversion signal of the inversion signal ZDD provides the output signal .phi.1 of an "H" level, as shown in FIG. 20(c), to the gate electrode of n channel MOS transistor 13c. Since n channel MOS transistor 13c is rendered conductive, and power supply potential node 11 and output node 13d are electrically connected, the output data Dour attains an "H" level as shown in FIG. 20(g). When the output enable signal OEM then falls from an "H" level to an "L" level at a time tl as shown in FIG. 20(b), the output data Dour again attains a high impedance state.
On the other hand, when data of the selected memory cell is at an "L" level, the inversion signal ZDD of the data is at an "H" level as shown in FIG. 21(a). AND circuit 13b receiving an inversion signal of the inversion signal ZDD provides the output signal .phi.1 of an "L" level, as shown in FIG. 21(c), independent of the level of the output enable signal OEM which is another input. n channel MOS transistor 13c receiving the output signal .phi.1 at the gate electrode is non-conductive. Until the output enable signal OEM rises to an "H" level at the time t0 as shown in FIG. 21(b), AND circuit 13e receiving the output enable signal OEM of an "L" level provides the output signal .phi.2 of an "L" level as shown in FIG. 21(d), rendering n channel MOS transistor 13f receiving the output signal .phi.2 at the gate electrode non-conductive. AND circuit 13h receiving the output signal .phi.2 of an "L" level provides the output signal .phi.4 of an "L", level, as shown in FIG. 21(f), to the gate electrode of n channel MOS transistor 13i, independent of the level of the delay signal .phi.3 from delay circuit 13g. Meantime, since n channel MOS transistor 13i is rendered non-conductive, the data Dour provided from output node 13d is in a high impedance state.
When the output enable signal OEM rises to an "H" level at the time t0 as shown in FIG. 21(b), AND circuit 13e receiving the output enable signal OEM and the inversion signal ZDD provides the output signal .phi.2 of an "H" level, as shown in FIG. 21(d), to the gate electrode of n channel MOS transistor 13f. Since n channel MOS transistor 13f is rendered conductive, and ground potential node 12 and output node 13d are electrically connected, the output data Dout begins to fall slowly as shown in FIG. 21(g).
Delay circuit 13g receiving the output signal .phi.2 from AND circuit 13e which rises to an "H" level at the time t0 provides the delay signal .phi.3 which rises to an "H" level at a time t2 delayed by a delay time td, as shown in FIG. 21(e), which is determined by the number of inverters configuring delay circuit 13g. AND circuit 13h receiving the delay signal .phi.3 and output signal .phi.2 from AND circuit 13e of an "H" level provides the output signal .phi.4 which rises to an "H" level, as shown in FIG. 21(f), to the gate electrode of n channel MOS transistor 13i. Since n channel MOS transistor 13i is rendered conductive, and ground potential node 12 and output node 13d are electrically connected, the output data Dour quickly attains the ground potential as shown in FIG. 21(g). When the output enable signal OEM then falls from an "H" level to an "L" level at a time t3 as shown in FIG. 21(b), the output data Dout again attains a high impedance state.
Undershoot and ringing are prevented from occurring at the time of discharge of output node 13d by delaying the timing to bring the output data Dout of output node 13d into the ground potential in two steps. The falling time of the output data Dout has its lower limit determined by specification. The output data Dour from data output portion 5d proximate to ground potential pad 3 quickly falls to the ground potential through n channel MOS transistor 13i, not only because the potential of power supply interconnection line 4 transmitting the ground potential does not rise from the ground potential GND in the vicinity of data output portion 5d, but also because an interconnection resistance from ground potential pad 3 is small. Therefore, in order to satisfy the lower limit of the specification, delay by delay circuit 13g becomes necessary.
As a conventional semiconductor memory device is made larger in storage capacity with the size of a chip increased, power supply interconnection line 4 transmitting the ground potential becomes longer, causing an interconnection resistance R1 and a parasitic capacitance C1 to increase as shown in FIG. 22. As a result, the longer the distance from ground potential pad 3 to which ground line 4 is connected, the less stable the ground potential which ground potential pad 3 transmits, whereby discharge of a data pin 15 distant from ground potential pad 3 to the ground potential through data output circuit 13 is made slow. Since data output circuit 13 provided in data output portions 5a to 5d has the same configuration independent of the distance from ground potential pad 3, an access speed is determined by the falling time to the ground potential of data pin 15 the most distant from ground potential pad 3 in a multi-bit configuration having a plurality of data output pins as shown in FIG. 18. Therefore, when ground line 4 transmitting the ground potential becomes longer and the ground potential becomes unstable, the access speed is decreased.
In order to shorten the falling time to the ground potential through data output circuit 13 distant from ground potential pad 3, it is considered that a delay time determined by delay circuit 13g in data output circuit 13 is shortened. However, in this case, since data output circuit 13 has the same configuration independent of the distance from ground potential pad 3, the delay time by delay circuit 13g of data output circuit 13 proximate to ground potential pad 3 is also shortened. There is a problem that the output data Dout from data output circuit 13 quickly falls to the ground potential, whereby undershoot and ringing are likely to occur.
The interconnection resistance, the parasitic capacitance and the parasitic inductance of ground line 4 are problematic in a power supply line transmitting the power supply potential vcc. As shown in FIG. 23, a power supply line 7 transmitting the power supply potential Vcc along a circumference of semiconductor chip 1 is provided in a loop manner. Power supply line 7 is provided at a circumferential end of semiconductor chip 1 to be connected to a power supply pad 6. Data output portions 5a to 5d are supplied with the power supply potential Vcc through power supply line 7 to carry out charge of output node 13d. In order to prevent overshoot and/or ringing at output node 13d (an output band and data output pin) at the time of charge of output node 13d, it is considered that charging operation is carried out in two steps in data output circuit 13.
Referring to FIG. 24, data output circuit 13 includes an inverter 13a receiving the data inversion signal ZDD, a 2-input AND circuit 13b receiving the output enable signal OEM and the output of inverter 13a, a 2-input AND circuit 13e receiving the output enable signal OEM and the data inversion signal ZDD, an n channel MOS transistor 13c charging output node 13d to a level of the power supply potential in response to an output of AND circuit 13b, and an n channel MOS transistor 13h discharging output node 13d to a level of the ground potential in response to an output of AND circuit 13e.
Data output circuit 13 further includes a delay circuit 13k delaying an output of AND circuit 13b by a predetermined time, a 2-input AND circuit 13l receiving an output of delay circuit 13k and an output of AND circuit 13b, and an n channel MOS transistor 13m charging output node 13d to a level of power supply potential in response to an output of AND circuit 13l.
MOS transistor 13m has a size and a current driving ability larger than those of MOS transistor 13c.
In the configuration shown in FIG. 24, when the output of AND circuit 13b rises, MOS transistor 13c is rendered conductive, causing output node 13d to be charged. After a predetermined time, the output of the delay circuit rises, and MOS transistor 13m is rendered conductive, causing output node 13d to be charged. Since output node 13d is charged in two steps, occurrence of overshoot and/or ringing can be prevented.
As for power supply line 7, distributed resistance and parasitic capacitance exist, as shown in FIG. 25. The interconnection resistance and the parasitic capacitance are, shown in FIG. 25 as a resistance R2 and a capacitance C2, respectively, connected between a power supply potential node 11 to which MOS transistors 13c and 13m are connected and a pad 6. The magnitude of resistance R2 and capacitance C2 is in proportion to the distance between pad 6 and data output circuit 13. As a result, data output circuit 13 has a charging time in accordance with the position thereof on semiconductor chip 1. A timing at which the output data Dout is decided is determined by the worst (longest) charging time (which is applied by a data output circuit the most distant from pad 6), causing the access time no be longer. A delay circuit is provided with a data output circuit proximate to pad 6. This is because the conditions of the specification which determines the lower limit of the rising time of the output data Dout are satisfied. Therefore, in the case where all data output circuits have the same configuration, there is a trade off between shortening of the access time and prevention of occurrence of overshoot/ringing.